Measuring setup and hold times of fabricated digital circuits may involve manual measurements, measurements using a tester device, or an on-chip tester using a finite state machine. Manual measurements may involve manually delaying a data signal with respect to a clock and recording an amount of delay when a device under test transitions from a pass status to a fail status. However, manual measurements may have a time consuming setup, have time consuming measurements, and utilize expensive hardware, such as a pulse generator with adjustable delay. A tester device may automatically delay a data signal with respect to a clock, thereby reducing measurement time. However, testers are extremely expensive and are still time consuming since data is physically delayed. An on-chip tester using a finite state machine may have a fast setup and a reduced measurement time. However, many on-chip testers use expensive hardware, such as, very sophisticated finite state machines, and digital and analog IP blocks. Moreover, such expensive hardware may occupy valuable space on a fabricated device.
A need therefore exists for methodology and an apparatus enabling reduced setup and measurement time without expensive hardware for measuring setup and hold times of fabricated semiconductor devices.